The present disclosure relates to semiconductor devices. To increase the integration density of nonvolatile semiconductor memory devices, research regarding a vertical-type NAND (VNAND) channel structure has been conducted. The VNAND string structure is described, for example, in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory” by H. Tanaka et al., VLSI Technology, 2007 IEEE Symposium on, pp. 14-15. Also, a vertical-type memory device with metal gates and a method of fabricating the same are disclosed in U.S. Patent Pub. No. 2009/121271, entitled “Vertical-type non-volatile memory devices”. The entire contents of these documents are incorporated by reference in the present patent application.